1. Field of the Invention
The present invention generally relates to the field of semiconductor devices, and more particularly, the present invention relates to etch stop structures and methods utilized in the manufacture of semiconductor devices.
2. Description of the Related Art
The use of etch stop layers in the manufacture of semiconductor devices is well known in the art. In addition to signaling the termination point of an etching process used to remove an overlying layer or layers, the etch stop layer functions to protect any underlying layer or layers during the etching process. However, one drawback encountered with the conventional use of etch stop layers occurs when an edge of the etch stop layer abuts against a conductive layer during wet etching of a layer formed over the etch stop layer. In this case, the etchant used in the wet etch process can permeate between the etch stop layer and the conductive layer, thus causing damage to the layer or layers underlying the etch stop layer. An example of this problem is presented below in the context of the manufacture of a cylindrical memory cell capacitor.
FIGS. 1A through 1F are schematic cross-sectional views for explaining a method of manufacturing a memory cell in which the lower electrode of the capacitor thereof has a cylindrical structure. Referring initially to FIG. 1A, a plurality of impurity regions (not shown) are formed in the surface of a semiconductor substrate 5. An interlayer dielectric (ILD) 10 is then formed over the substrate 5, and contact pad holes 15 are selectively etched in the ILD 10 to expose the respective impurity regions. The contact holes 15 are then filled with respective contact pads 20. Then, a first etch stop layer 25, a support insulator layer 30, a second etch stop layer 35, a mold layer 40, and an anti-reflection film 45 are successively formed over the ILD 10 as shown. The first and second etch stop layers 25 and 35 are typically formed of silicon nitride (Si3N4).
Then, as illustrated in FIG. 1B, a photoresist film pattern 50 is formed over the anti-reflection film 45, and thereafter the anti-reflection film 45, the mold layer 40, the second etch stop layer 35, the support insulator layer 30, and the first etch stop layer 25 are all etched to define node holes 55 which expose the respective contact pads 20. Here, the etching process typically both dry etch and wet etch processes. In this case, referring to FIG. 1C, sidewall portions of the mold layer 40 and support insulator layer 30 may be eroded, resulting in the protrusion of the exposed edges of the first and second etch stop layers 25 and 35. Likewise, an upper surface portion of the ILD 10 may be removed by the wet etching, resulting in the protrusion of the upper end of the contact pad 20 from the surface of the ILD 10.
Referring still to FIG. 1C, a storage node 60 is conformably formed on sidewall and bottom walls of the node hole 55 (FIG. 1B). The storage node 60 is typically form of titanium nitride (TiN). Then, a sacrificial layer 65 is formed on the resultant structure to as to fill the node hole 55.
Then, as illustrated in FIG. 1D, the sacrificial layer 65 and the storage node 60 are planarized (typically by CMP) to expose the upper surface portion of the mold layer 40. In FIG. 1D, the planarized sacrificial layer is identified by reference number 75, and the planarized storage node is identified by reference number 70.
Referring next to FIG. 1E, a wet etch process is executed to remove the mold layer 40 (FIG. 1D) and the sacrificial layer 75 (FIG. 1D). The wet etchant used in this process must exhibit etch selectivity with respect to the storage node 70 and the silicon nitride etch stop layer 35. Unfortunately, however, in practice the silicon nitride etch stop layers 35 and 25 are easily eroded by the wet etchant used to remove the mold and sacrificial layers. As a result, referring to reference numbers A1 and A2 of FIG. 1E, the wet etchant tends to permeate between the storage node 70 and the etch stop layers 35 and 25, thus damaging the underlying insulating layer 30 and ILD 10, respectively.
Turing now to FIG. 1F, the memory cell is essentially completed by conformally depositing a dielectric layer 80 on the exposed surfaces of the storage node 70, and by then forming a plate node layer 85 on the resultant structure as shown. Note that the capacitive element 90 of the memory cell is constituted by the storage node 70, the dielectric layer 80, and the plate node layer 85.
As described above, the use of conventional etch stop layers may result in fabrication problems. For example, problems occur when an edge of a conventional etch stop layer abuts against a conductive layer during wet etching of a layer formed over the etch stop layer. In the case of fabricating a cylindrical capacitor electrode, the wet etchant may permeate between the etch stop layer and a storage node during removal of mold and sacrificial layers, thus causing damage to the layer or layers underlying the etch stop layer.